|Designed by||ARM Holdings|
|L1 cache||32 KiB/32 KiB|
|L2 cache||512 KiB|
Compared to the ARM11 core, the Cortex-A8 is a dual-issue superscalar design, achieving roughly twice the instructions executed per clock cycle. The Cortex-A8 was the first Cortex design to be adopted on a large scale for use in consumer devices.
Key features of the Cortex-A8 core are:
- Frequency from 600 MHz to 1 GHz and above
- Superscalar dual-issue microarchitecture
- NEON SIMD instruction set extension 
- 13-stage integer pipeline and 10-stage NEON pipeline 
- VFPv3 Floating Point Unit
- Thumb-2 instruction set encoding
- Jazelle RCT (Also known as ThumbEE instruction set)
- Advanced branch prediction unit with >95% accuracy
- Integrated level 2 Cache (0–4 MiB)
- 2.0 DMIPS/MHz
Several system-on-chips (SoC) have implemented the Cortex-A8 core, including:
- Gupta, Rahul (April 26, 2013). "ARM Cortex: The force that drives mobile devices". The Mobile Indian. Retrieved 2013-05-15.
- Cortex-A8 Specification Summary; ARM Holdings.
- Williamson, David, ARM Cortex A8: A High Performance Processor for Low Power Applications (PDF), archived from the original (PDF) on 2015-01-01
- "i.MX51 Applications Processor and Linux Hands on" (PDF).
- "RK29XX". Archived from the original on 2011-11-05.
- "CX97255" (PDF). Archived from the original (PDF) on 2012-11-19.