5 nm process

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In semiconductor manufacturing, the International Roadmap for Devices and Systems defines the nm process as the MOSFET technology node following the 7 nm node. In 2020, Samsung and TSMC entered volume production of 5 nm chips, manufactured for companies including Apple, Marvell, Huawei and Qualcomm.[1][2]

The commercial 5 nm node is based on multi-gate MOSFET (MuGFET) technology, with FinFETs (fin field-effect transistors). 5 nm GAAFET (gate-all-around field-effect transistor) nodes had also been demonstrated, but not commercialized.



Transistors smaller than 7 nm will experience quantum tunnelling through the gate oxide layer.[3] Single-transistor devices below 7 nm were first demonstrated by researchers in the early 2000s. In 2002, an IBM research team including Bruce Doris, Omer Dokumaci, Meikei Ieong and Anda Mocuta fabricated a 6-nanometre silicon-on-insulator (SOI) MOSFET.[4][5]

In 2003, a Japanese research team at NEC, led by Hitoshi Wakabayashi and Shigeharu Yamagami, fabricated the first 5 nm MOSFET.[6][7]

In 2015, IMEC and Cadence had fabricated 5 nm test chips. The fabricated test chips are not fully functional devices but rather are to evaluate patterning of interconnect layers.[8][9]

In 2015, Intel described a lateral nanowire (or gate-all-around) FET concept for the 5 nm node.[10]

In 2017, IBM revealed that they had created 5 nm silicon chips,[11] using silicon nanosheets in a gate-all-around configuration (GAAFET), a break from the usual FinFET design. The GAAFET transistors used had 3 nanosheets stacked on top of each other, covered in their entirety by the same gate, just like FinFETs usually have several physical fins side by side that are electrically a single unit and are covered in their entirety by the same gate. IBM's chip measured 50 mm2 and had 600 million transistors per mm2.[12][13]


In April 2019, Samsung Electronics announced they had been offering their 5 nm process (5LPE) tools to their customers since 2018 Q4.[14] In April 2019, TSMC announced that their 5 nm process (CLN5FF, N5) had begun risk production, and that full chip design specifications were now available to potential customers. The N5 process can use EUVL on up to 14 layers, compared to only 5 or 4 layers in N6 and N7++.[15]

In October 2019, TSMC started sampling 5nm A14 processors for Apple.[16]

In December 2019, TSMC announced an average yield of ~80%, with a peak yield per wafer of >90% for their 5nm test chips with a die size of 17.92 mm2.[17] In mid 2020 TSMC claimed its (N5) 5nm process offered 1.8x the density of its 7nm N7 process, with 15% speed improvement or 30% lower power consumption; am improved sub-version (N5P) was claimed to improve on N5 with +5% speed or -10% power.[18]

On October 13 2020, Apple announced a new iPhone lineup using the A14, the first devices to be commercialized on TSMC's 5nm node.

5 nm process nodesEdit

Samsung[19] TSMC[20] IRDS roadmap 2017[21]
Process name (nm) 5LPE N5 7 5
Transistor density (MTr/mm2) 127 173[22] ? ?
SRAM bit-cell size (μm2) 0.026 0.017–0.019 0.027[23] 0.020[23]
Transistor gate pitch (nm) 57 48 48 42
Interconnect pitch (nm) 36 30 28 24
Risk production year 2018[14] 2019[15] 2019 2021

Transistor gate pitch is also referred to as CPP (contacted poly pitch) and interconnect pitch is also referred to as MMP (minimum metal pitch).[24][25]

Beyond 5 nmEdit

3 nm (3-nanometer) is the usual term for the next node after 5 nm. As of 2020, Samsung and TSMC have plans to commercialize the 3 nm node.

3.5 nm has also been given as a name for the first node beyond 5 nm.[26]


  1. ^ Cutress, Dr Ian. "'Better Yield on 5nm than 7nm': TSMC Update on Defect Rates for N5". www.anandtech.com. Retrieved 2020-08-28.
  2. ^ "Marvell and TSMC Collaborate to Deliver Data Infrastructure Portfolio on 5nm Technology". HPCwire. Retrieved 2020-08-28.
  3. ^ "Quantum Effects At 7/5nm And Beyond". Semiconductor Engineering. Retrieved 2018-07-15.
  4. ^ "IBM claims world's smallest silicon transistor - TheINQUIRER". Theinquirer.net. 2002-12-09. Retrieved 7 December 2017.
  5. ^ Doris, Bruce B.; Dokumaci, Omer H.; Ieong, Meikei K.; Mocuta, Anda; Zhang, Ying; Kanarsky, Thomas S.; Roy, R. A. (December 2002). "Extreme scaling with ultra-thin Si channel MOSFETs". Digest. International Electron Devices Meeting: 267–270. doi:10.1109/IEDM.2002.1175829. ISBN 0-7803-7462-2. S2CID 10151651.
  6. ^ "NEC test-produces world's smallest transistor". Thefreelibrary.com. Retrieved 7 December 2017.
  7. ^ Wakabayashi, Hitoshi; Yamagami, Shigeharu; Ikezawa, Nobuyuki; Ogura, Atsushi; Narihiro, Mitsuru; Arai, K.; Ochiai, Y.; Takeuchi, K.; Yamamoto, T.; Mogami, T. (December 2003). "Sub-10-nm planar-bulk-CMOS devices using lateral junction control". IEEE International Electron Devices Meeting 2003: 20.7.1–20.7.3. doi:10.1109/IEDM.2003.1269446. ISBN 0-7803-7872-5. S2CID 2100267.
  8. ^ "IMEC and Cadence Disclose 5nm Test Chip". Semiwiki.com. Retrieved 25 Nov 2015.
  9. ^ "The Roadmap to 5nm: Convergence of Many Solutions Needed". Semi.org. Archived from the original on 26 November 2015. Retrieved 25 November 2015.
  10. ^ Mark LaPedus (2016-01-20). "5nm Fab Challenges". Intel presented a paper that generated sparks and fueled speculation regarding the future direction of the leading-edge IC industry. The company described a next-generation transistor called the nanowire FET, which is a finFET turned on its side with a gate wrapped around it. Intel's nanowire FET, sometimes called a gate-all-around FET, is said to meet the device requirements for 5nm, as defined by the International Technology Roadmap for Semiconductors (ITRS).
  11. ^ Sebastian, Anthony. "IBM unveils world's first 5nm chip". Ars Technica. Retrieved 2017-06-05.
  12. ^ Zafar, Ramish (June 5, 2017). "It's Official: IBM Launches The 5nm GAAFET Chip With 30 Billion Transistors Per 50mm², 75% Power & 40% Performance Boost".
  13. ^ "IBM Figures Out How to Make 5nm Chips". Uk.pcmag.com. 5 June 2017. Retrieved 7 December 2017.
  14. ^ a b Shilov, Anton. "Samsung Completes Development of 5nm EUV Process Technology". anandtech.com. Retrieved 2019-05-31.
  15. ^ a b TSMC and OIP Ecosystem Partners Deliver Industry's First Complete Design Infrastructure for 5nm Process Technology (press release), TSMC, 3 April 2019
  16. ^ Solca, Bogdan. "TSMC already sampling Apple's 5 nm A14 Bionic SoCs for 2020 iPhones". Notebookcheck.
  17. ^ Cutress, Dr Ian. "Early TSMC 5nm Test Chip Yields 80%, HVM Coming in H1 2020". www.anandtech.com.
  18. ^ Hruska, Joel (25 Aug 2020), "TSMC Plots an Aggressive Course for 3nm Lithography and Beyond", www.extremetech.com
  19. ^ Jones, Scotten, 7nm, 5nm and 3nm Logic, current and projected processes
  20. ^ Schor, David (2019-04-06). "TSMC Starts 5-Nanometer Risk Production". WikiChip Fuse. Retrieved 2019-04-07.
  21. ^ "IRDS international roadmap for devices and systems 2017 edition" (PDF). Archived from the original (PDF) on 2018-10-25.
  22. ^ Jones, Scotten (May 3, 2019). "TSMC and Samsung 5nm Comparison". Semiwiki. Retrieved 30 July 2019.
  23. ^ a b INTERNATIONAL ROADMAP FOR DEVICES AND SYSTEMS 2017 EDITION - MORE MOORE (PDF), ITRS, 2017, Section 4.5 Table MM-10 (p.12) entries : "SRAM bitcell area (um2)" ; "SRAM 111 bit cell area density - Mbits/mm2", archived from the original (PDF) on 2018-10-25, retrieved 2018-10-24
  24. ^ "International Technology Roadmap for Semiconductors 2.0 2015 Edition Executive Report" (PDF). Semiconductors.org. Archived from the original (PDF) on 2 October 2016. Retrieved 7 December 2017.
  25. ^ "5 nm lithography process". En.wikichip.org. Retrieved 7 December 2017.
  26. ^ "15 Views from a Silicon Summit: Macro to nano perspectives of chip horizon". EETimes.com. 16 January 2017. Retrieved 4 June 2018.

Preceded by
7 nm (FinFET)
MOSFET semiconductor device fabrication process Succeeded by
3 nm