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In semiconductor manufacturing, the International Roadmap for Devices and Systems defines the 5 nanometer (5 nm) node as the MOSFET technology node following the 7 nm node. As of 2019, Samsung Electronics and TSMC have begun commercial production of 5 nm nodes.

5 nm nodes are based on multi-gate MOSFET (MuGFET) technology. The two types of MuGFET technology used at 5 nm are the FinFET (fin field-effect transistor) and the GAAFET (gate-all-around field-effect transistor).



The 5 nm node was once assumed by some experts to be the end of Moore's law.[1] Transistors smaller than 7 nm will experience quantum tunnelling through the gate oxide layer.[2] Due to the costs involved in development, 5 nm is predicted to take longer to reach market than the two years estimated by Moore's law.[1]

Beyond 7 nm, it was initially claimed that major technological advances would have to be made to produce chips at this small scale.[citation needed] In particular, it is believed[according to whom?] that 5 nm may usher in the successor to the FinFET, such as a gate-all-around architecture.[citation needed]

In 2009, Intel's roadmap projected an end-user release by approximately 2020, though Intel has not yet revealed any specific plans to manufacturers or retailers.[3][4]

Technology demosEdit

Single-transistor devices below 7 nm were first demonstrated by researchers in the early 2000s. In 2002, an IBM research team including Bruce Doris, Omer Dokumaci, Meikei Ieong and Anda Mocuta fabricated a 6 nanometer silicon-on-insulator (SOI) MOSFET.[5][6]

In 2003, a Japanese research team at NEC, led by Hitoshi Wakabayashi and Shigeharu Yamagami, fabricated the first 5 nm MOSFET.[7][8]

In 2015, IMEC and Cadence had fabricated 5 nm test chips. The fabricated test chips are not fully functional devices but rather are to evaluate patterning of interconnect layers.[9][10]

In 2015, Intel described a lateral nanowire (or gate-all-around) FET concept for the 5 nm node.[11]

In 2017, IBM revealed that they had created 5 nm silicon chips,[12] using silicon nanosheets in a gate-all-around configuration (GAAFET), a break from the usual FinFET design.[13]


In early 2018, TSMC announced production of a 5 nm node by 2020 on its new Fab 18.[14] In October 2018, TSMC disclosed plans to start risk production of 5 nm devices by April 2019.[15]

In April 2019, Samsung Electronics announced they had been offering their 5 nm process (5LPE) tools to their customers since 2018 Q4.[16] In April 2019, TSMC announced that their 5 nm process (CLN5FF, N5) had begun risk production, and that full chip design specifications were now available to potential customers. The N5 process can use EUVL on up to 14 layers, compared to only 5 or 4 layers in N6 and N7++.[17]

5 nm process nodesEdit

Samsung [18] TSMC [19] IRDS roadmap 2017[20]
Process name (nm) 5LPE N5 7 5
Transistor density (MTr/mm2) 126.53 173.1[21] 222 (37x6) [22] 300 (50x6) [22]
SRAM bit-cell size (µm²) 0.0262 0.017-0.019 0.0269[22] 0.0202[22]
Transistor gate pitch (nm) 57 48 48 42
Interconnect pitch (nm) 36 30 28 24
Production year 2018[16] 2019[17] 2019 2021
† Based on a 6T SRAM 111 cell

Transistor gate pitch is also referred to as CPP (contacted poly pitch) and interconnect pitch is also referred to as MMP (minimum metal pitch).[23][24]

Beyond 5 nmEdit

"3 nm" (3 nanometer) is the usual term for the next node after 5 nm. As of 2019 Samsung and TSMC have plans to commercialize the 3 nm node.

3.5 nm has also been given as a name for the first node beyond 5 nm.[25]


  1. ^ a b "End of Moore's Law: It's not just about physics". CNET. August 28, 2013.
  2. ^ "Quantum Effects At 7/5nm And Beyond". Semiconductor Engineering. Retrieved 2018-07-15.
  3. ^ "Intel Outlines Process Technology Roadmap". Xbit. 2009-08-22. Archived from the original on 2011-05-28.
  4. ^ "インテル、32nmプロセスの順調な立ち上がりをアピール" [Intel touts steady rise of 32 nm processors] (in Japanese). PC Watch. 2009-08-21.
  5. ^ "IBM claims world's smallest silicon transistor - TheINQUIRER". 2002-12-09. Retrieved 7 December 2017.
  6. ^ Doris, Bruce B.; Dokumaci, Omer H.; Ieong, Meikei K.; Mocuta, Anda; Zhang, Ying; Kanarsky, Thomas S.; Roy, R. A. (December 2002). "Extreme scaling with ultra-thin Si channel MOSFETs". Digest. International Electron Devices Meeting: 267–270. doi:10.1109/IEDM.2002.1175829.
  7. ^ "NEC test-produces world's smallest transistor". Retrieved 7 December 2017.
  8. ^ Wakabayashi, Hitoshi; Yamagami, Shigeharu; Ikezawa, Nobuyuki; Ogura, Atsushi; Narihiro, Mitsuru; Arai, K.; Ochiai, Y.; Takeuchi, K.; Yamamoto, T.; Mogami, T. (December 2003). "Sub-10-nm planar-bulk-CMOS devices using lateral junction control". IEEE International Electron Devices Meeting 2003: 20.7.1–20.7.3. doi:10.1109/IEDM.2003.1269446.
  9. ^ "IMEC and Cadence Disclose 5nm Test Chip". Retrieved 25 Nov 2015.
  10. ^ "The Roadmap to 5nm: Convergence of Many Solutions Needed". Archived from the original on 26 November 2015. Retrieved 25 November 2015.
  11. ^ Mark LaPedus (2016-01-20). "5nm Fab Challenges". Intel presented a paper that generated sparks and fueled speculation regarding the future direction of the leading-edge IC industry. The company described a next-generation transistor called the nanowire FET, which is a finFET turned on its side with a gate wrapped around it. Intel's nanowire FET, sometimes called a gate-all-around FET, is said to meet the device requirements for 5nm, as defined by the International Technology Roadmap for Semiconductors (ITRS).
  12. ^ Sebastian, Anthony. "IBM unveils world's first 5nm chip". Ars Technica. Retrieved 2017-06-05.
  13. ^ "IBM Figures Out How to Make 5nm Chips". 5 June 2017. Retrieved 7 December 2017.
  14. ^ "TSMC Breaks Ground on Fab 18 in Southern Taiwan Science Park".
  15. ^ Shilov, Anton. "TSMC: First 7nm EUV Chips Taped Out, 5nm Risk Production in Q2 2019".
  16. ^ a b Shilov, Anton. "Samsung Completes Development of 5nm EUV Process Technology". Retrieved 2019-05-31.
  17. ^ a b TSMC and OIP Ecosystem Partners Deliver Industry’s First Complete Design Infrastructure for 5nm Process Technology (press release), TSMC, 3 April 2019
  18. ^ Jones, Scotten, 7nm, 5nm and 3nm Logic, current and projected processes
  19. ^ Schor, David (2019-04-06). "TSMC Starts 5-Nanometer Risk Production". WikiChip Fuse. Retrieved 2019-04-07.
  20. ^ "IRDS international roadmap for devices and systems 2017 edition" (PDF).
  21. ^ Jones, Scotten (May 3, 2019). "TSMC and Samsung 5nm Comparison". Semiwiki. Retrieved 30 July 2019.
  23. ^ "International Technology Roadmap for Semiconductors 2.0 2015 Edition Executive Report" (PDF). Archived from the original (PDF) on 2 October 2016. Retrieved 7 December 2017.
  24. ^ "5 nm lithography process". Retrieved 7 December 2017.
  25. ^ "15 Views from a Silicon Summit: Macro to nano perspectives of chip horizon". 16 January 2017. Retrieved 4 June 2018.

Preceded by
7 nm (FinFET)
MOSFET manufacturing processes Succeeded by
3 nm (GAAFET)