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The 250 nanometer (250 nm or 0.25 µm) process refers to a level of MOSFET (CMOS) semiconductor process technology that was commercialized by semiconductor manufacturers around the 1996–1998 timeframe.

A 250 nm CMOS process was demonstrated by a Japanese NEC research team led by Naoki Kasai in 1987.[1] In 1988, an IBM research team led by Iranian engineer Bijan Davari fabricated a 250 nm dual-gate MOSFET using a CMOS process.[2]

Products featuring 250 nm manufacturing processEdit


Preceded by
350 nm
CMOS manufacturing processes Succeeded by
180 nm

ReferencesEdit

  1. ^ Kasai, Naoki; Endo, Nobuhiro; Kitajima, Hiroshi (December 1987). "0.25 µm CMOS technology using P+polysilicon gate PMOSFET". 1987 International Electron Devices Meeting: 367–370. doi:10.1109/IEDM.1987.191433.
  2. ^ Davari, Bijan; et al. (1988). "A high-performance 0.25 micrometer CMOS technology". International Electron Devices Meeting.
  3. ^ a b c d "Memory". STOL (Semiconductor Technology Online). Retrieved 25 June 2019.