The 22 nanometer (22 nm) node is the process step following the 32 nm in CMOS semiconductor device fabrication. The typical half-pitch (i.e., half the distance between identical features in an array) for a memory cell using the process is around 22 nm. It was first demonstrated by semiconductor companies for use in RAM memory in 2008. In 2010, Toshiba began shipping 24 nm flash memory chips, and Samsung Electronics began mass-producing 20 nm flash memory chips. The first consumer-level CPU deliveries using a 22 nm process started in April 2012.
The ITRS 2006 Front End Process Update indicates that equivalent physical oxide thickness will not scale below 0.5 nm (about twice the diameter of a silicon atom), which is the expected value at the 22 nm node. This is an indication that CMOS scaling in this area has reached a wall at this point, possibly disturbing Moore's law.
20 nanometer is an intermediate half-node die shrink based on the 22 nanometer process.
In December 2000, a 20 nm FinFET process was described by Digh Hisamoto from Hitachi Central Research Laboratory with UC Berkeley researchers Chenming Hu, Tsu-Jae King-Liu, Jeffrey Bokor, Wen-Chin Lee, Jakub Kedzierski, Hideki Takeuchi, Kazuya Asano, Charles Kuo, and Erik Anderson.
On August 18, 2008, AMD, Freescale, IBM, STMicroelectronics, Toshiba, and the College of Nanoscale Science and Engineering (CNSE) announced that they jointly developed and manufactured a 22 nm SRAM cell, built on a traditional six-transistor design on a 300 mm wafer, which had a memory cell size of just 0.1 μm2. The cell was printed using immersion lithography.
The 22 nm node may be the first time where the gate length is not necessarily smaller than the technology node designation. For example, a 25 nm gate length would be typical for the 22 nm node.
On September 22, 2009, during the Intel Developer Forum Fall 2009, Intel showed a 22 nm wafer and announced that chips with 22 nm technology would be available in the second half of 2011. SRAM cell size is said to be 0.092 μm2, smallest reported to date.
- Toshiba announced that it was shipping 24 nm flash memory NAND devices on August 31, 2010.
- In 2010, Samsung Electronics began mass production of 64 Gb NAND flash memory chips using a 20 nm process.
- Also in 2010, Hynix introduced a 64 Gb NAND flash memory chip using a 20 nm process.
- On April 23, 2012, Intel Core i7 and Intel Core i5 processors based on Intel's Ivy Bridge 22 nm technology for series 7 chipsets went on sale worldwide. Volume production of 22 nm processors began more than six months earlier, as confirmed by former Intel CEO Paul Otellini on October 19, 2011.
- On June 3, 2013, Intel started shipping Intel Core i7 and Intel Core i5 processors based on Intel's Haswell microarchitecture in 22 nm Tri-Gate FinFET technology for series 8 chipsets.
- "20nm Technology". TSMC. Retrieved 30 June 2019.
- Hisamoto, Digh; Hu, Chenming; et al. (December 2000). "FinFET-a self-aligned double-gate MOSFET scalable to 20 nm". IEEE Transactions on Electron Devices. 47 (12): 2320–2325. CiteSeerX 10.1.1.211.204. doi:10.1109/16.887014.
- "TG Daily news report". Archived from the original on 2008-08-19. Retrieved 2008-08-18.
- EETimes news report
- Intel announces 22nm chips for 2011
- Intel 22nm 3-D Tri-Gate Transistor Technology
- IBM opens Power8 kimono (a little bit more)
- Toshiba launches 24nm process NAND flash memory
- "History". Samsung Electronics. Samsung. Retrieved 19 June 2019.
- "History: 2010s". SK Hynix. Retrieved 8 July 2019.
- Intel launches Ivy Bridge...
- Tom's Hardware: Intel to Sell Ivy Bridge Late in Q4 2011
- "4th Generation Intel® Core™ Processors Coming Soon". Archived from the original on 2015-02-09. Retrieved 2013-04-27.
32 nm (CMOS)
|MOSFET manufacturing processes||Succeeded by|
14 nm (FinFET)