Intel HD Graphics

Core i5 processor with integrated HD Graphics 2000

Intel HD Graphics is a series of Intel integrated graphics processors built into computer processors.

History

Before the introduction of Intel HD Graphics, Intel integrated graphics were built into the motherboard's northbridge. This included Intel Extreme Graphics and the Intel Graphics Media Accelerator. As part of the Platform Controller Hub (PCH) design, the northbridge was eliminated and graphics processing was moved to the central processing unit (CPU).

In January 2010, the Clarkdale and Arrandale processors were released with HD Graphics, and branded as Celeron, Pentium, or Core.

In January 2011, the Sandy Bridge processors were released, introducing the "second generation" HD Graphics:

  • HD Graphics (6 execution units)
  • HD Graphics 2000 (6 execution units)
  • HD Graphics 3000 (12 execution units)

On April 24, 2012, Ivy Bridge was released, introducing the "third generation" HD Graphics:[1]

  • HD Graphics (6 execution units)
  • HD Graphics 2500 (6 execution units)
  • HD Graphics 4000 (16 execution units)

On September 12, 2012, Haswell was announced, with 4 models :

  • HD Graphics (GT1, 6 execution units)
  • HD Graphics 4200, 4400, 4600, P4600, P4700 (GT2, 20 execution units)
  • HD Graphics 5000, Iris Graphics 5100 (GT3, 40 execution units, twice the power-performance of HD4xxx for compute-limited workloads)
  • Iris Pro Graphics 5200 (GT3e, Same as previous, but with addition of large embedded DRAM cache to improve performance of bandwidth-limited workloads)
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Specifications

Main article: Comparison of Intel graphics processing units

Three active displays

See also: Digital_Visual_Interface#Clock_and_data_relationship

Ivy Bridge HD2500 and HD4000 chipsets are advertised as supporting three active monitors but many users have found that this does not work for them due to the chipset only supporting two active monitors in many common configurations.[2] The reason for this is that the chipset only includes two PLLs; a PLL generates a pixel clock at a certain frequency which is used to sync the timings of data being transferred between the GPU and displays.[2] Therefore, three simultaneously active monitors can only be achieved by a hardware configuration that requires only two unique pixel clocks, such as:

  • Using 2 or 3 active DisplayPort connections.[3] DisplayPort requires only a single pixel clock for all active connections, regardless of how many there are (this is not the case for non-active connections, which would require an extra pixel clock for each connection)
  • By using two non-DisplayPort connections of the same connection type (ie. HDMI+HDMI) and same clock frequency (ie. connected to two identical monitors at the same resolution) so that a single unique pixel clock can be shared between both connections.[4]
  • Using the Embedded DisplayPort on a mobile CPU along with any two other outputs.[3]
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See also

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References

  1. ^ "Intel's Official Ivy Bridge CPU Announcement Finally Live". 
  2. ^ a b LG Nilsson (2012-03-12). "Most desktop Ivy Bridge systems won't support three displays". VRZone. "Despite the fact that Intel has been banging its drums about support for up to three displays on the upcoming 7-series motherboards in combination with a shiny new Ivy Bridge based CPU, this isn't likely to be the case. The simple reason behind this is that very few, if any motherboards will sport a pair of DisplayPort connectors." 
  3. ^ a b David Galus (2013-02). "Migration to New Display Technologies on Intel Embedded Platforms". Intel. "The Intel® 7 Series Chipset based platform allows for the support of up to three concurrent displays with independent or replicated content. However, this comes with the requirement that either one of the displays is eDP running off the CPU or two DP interfaces are being used off the PCH. When configuring the 2 DP interfaces from the PCH, one may be an eDP if using Port D. This limitation exists because the 7 Series Intel PCH contains only two display PLLs (the CPU has one display PLL also) which will control the clocking for the respective displays. All display types other than DP have an external variable clock frequency associated with the display resolution that is being used. The DP interface has an embedded clocking scheme that is semi- variable, either at 162 or 270 MHz depending on the bandwidth required. Therefore, Intel only allows sharing of a display PLL with DP related interfaces." 
  4. ^ Michael Larabel (2011-10-06). "Details On Intel Ivy Bridge Triple Monitor Support". "A limitation of this triple monitor support for Ivy Bridge is that two of the pipes need to share a PLL. Ivy Bridge has three planes, three pipes, three transcoders, and three FDI (Flexible Display Interface) interfaces for this triple monitor support, but there's only two pipe PLLs. This means that two of the three outputs need to have the same connection type and same timings. However, most people in a triple monitor environment will have at least two -- if not all three -- of the monitors be identical and configured the same, so this shouldn't be a terribly huge issue." 
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Last modified on 17 May 2013, at 08:46